This invention relates to a digital convergence correction circuit for a display apparatus using a CRT (cathode ray tube), and more particularly to a display apparatus based on a digital convergence scheme suitably used as a display unit of the multi-scanning projection type or direct-view type.
Conventional projection display units generally include a horizontal arrangement of three projection tubes for red, green and blue along with respective projection lenses, and operate to compose a projected color image on a screen. Among the three color images, the red image and blue image are projected askew on the screen, and therefore a trapezoid distortion pertinent to the projective geometry emerges as shown in FIG. 1, causing the development of a color displacement.
A conventional manner of correcting the color displacement is to equip a convergence yoke for ancillary deflection of the electron beam, which is similar to the deflection yoke, on the neck of each projection tube, with the output of the convergence amplifier being applied to the convergence yoke. The correction signal applied to the convergence yoke is preferably synchronous with the deflection scanning and capable of correcting a color displacement pattern accurately.
Conventional correction waveform generation means are based on an analog scheme or digital scheme. The analog scheme is simple, but has a drawback of a poor accuracy. The digital scheme has a high correction accuracy, but has a drawback of expensiveness due to the need of a capacious memory. There is a method of reducing the memory capacity by assessing a frame of picture in terms of about 16-by-16 representative points (also called lattice points) and storing only corrective information for the representative points, with remaining areas being assessed through the interpolation based on the data of the representative points, as described in U.S. Pat. No. 4,422,019 (patented in 1983) and Japanese Patent Publication No. 61-55310.
The convergence signal generation circuit described in the above-mentioned patent publications is designed to produce the correction signal through the interpolation in the horizontal direction by means of a usual low-pass filter and conducting the calculation of interpolation in digital manner or analog manner in the vertical direction. Although this conventional technique is suited to a specific scanning format, it has a drawback of needing a large memory capacity when applied to a "multi-scan display unit" which is operative in various display formats, e.g., different horizontal frequencies and different screen sizes. Another problem is the need of a great deal of adjustment.
The above-mentioned problems will be explained in detail with reference to FIG. 2. The figure shows the arrangement of the conventional display unit based on a digital convergence scheme. Bold lines with arrows represent digital signals and single lines with arrows represent analog signals or 1-bit digital signals.
Indicated by 1 is an input terminal for the horizontal flyback pulse signal, 2 is a phase detector (.DELTA..phi.), 3 is a voltage-controlled oscillator (VCO), and 4 is a horizontal address signal generation counter (HAD). These blocks 2, 3 and 4 constitute a PLL (phase-locked loop) circuit known in the art. The counter 4 produces a 4-bit horizontal address signal X having a frequency 16 times the input horizontal scanning frequency. Indicated by 5 is a input vertical flyback pulse signal, and 6 is a vertical address signal generation counter (VAD). The counter 6 counts horizontal flyback pulses supplied to the input terminal 1 and produces vertical address signals Y and y. The signal Y is an upper 4-bit vertical address signal and the signal y is a lower 8-bit vertical address signal. Both signals Y and y have their values reset to zero in response to the reception of the vertical flyback pulse signal 5. The vertical address signal generation counter 6 has another input which is the maximum value y.sub.M of y provided by an address signal generator (GEN) 12 which will be explained shortly. A section of the counter 6 which deals with the lower eight bits of vertical address signal is cleared to the initial position (zero) each time the counter output arrives at y.sub.M, with the output value Y being incremented by one in this event.
FIG. 3 is a diagram used to explain a lattice pattern. The horizontal address X and vertical address Y in combination form coordinates of a representative lattice point on the screen. In the lattice patterns of FIG. 3, a portion shown by solid lines is an effective display area, and a portion shown by dashed lines is an over-scan section or flyback period section. The value y.sub.M is the number of scanning lines within a lattice segment in the vertical direction, and it is determined depending on the format (horizontal frequency, vertical frequency, number of scanning lines, etc.) of the input signal to the display unit. For example, for systems with 1000, 800, 600 and 450 scanning lines, the y.sub.M has approximate values of 80, 60, 50 and 38, respectively.
Returning to FIG. 2, indicated by 7, 8 and 9 are input selection switches, 10 is an E.sup.2 PROM (electrically erasable and programmable read only memory), 11 is a microprocessor, and 12 and 13 are an address signal generator (GEN) and vertical linear interpolator (VLI) included in the microprocessor 11. Indicated by 14 is a set of capacious E.sup.2 PROMs, 15 is a D/A converter, 16 is an amplifier, 17 is a CRT, 18 is a vertical ancillary deflection coil, and 19 is a horizontal ancillary deflection coil. The ancillary deflection coils 18 and 19 constitute the convergence yoke mentioned previously. The components 14-17 shown in the figure are only for one color, and the same set of components not shown in the figure is used for the remaining two colors. Other components 1-13 are used commonly for three colors (red, green and blue).
The capacious E.sup.2 PROM 14 needs a capacity for a format of about 1000 scanning lines as follows. EQU 1000.times.16.times.12 bits.times.2 directions.times.3 colors.perspectiveto.1.2M bits
Accordingly, a multi-scan display unit which deals with as many as 20 kinds of formats necessitates expensive E.sup.2 PROMs with a total capacity 20 times as much as the above estimation result, i.e., about 24M bits.
FIG. 3 explains the lattice pattern of the conventional display unit based on a digital convergence scheme.
The E.sup.2 PROM 10 stores only data of 16-by-12 (192) lattice points on the lattice pattern of FIG. 3. Each lattice point has 8-bit data for two directions (horizontal and vertical) and for three colors (red, green and blue). Accordingly, the total capacity needed for a format is:
8 bits.times.192.times.2 directions.times.3 colors.perspectiveto.10K bits That is, it is small capacity of 10K bits/1 format.
The convergence adjustment for each input signal format is carried out during the manufacturing process. After the adjustment has been completed, the display unit is ready to operate with its input selection switches 7, 8 and 9 all set to the left position in FIG. 2. Accordingly, portions including the blocks 10-13 are inactive. The counters 4 and 6 have their output address signals X, Y and y applied to the E.sup.2 PROM 14, which then reads out data corresponding to the input signal format. The output data are converted into analog signals by the D/A converter 15, and the resulting signals are fed through the amplifier 16 and applied to the ancillary deflection coils 18 and 19 (horizontal and vertical) of the CRT 17.
During the convergence adjustment in the manufacturing process of the display unit, data stored in address locations of the E.sup.2 PROM 10 for solid line lattice points (X, Y) shown in FIG. 3 are revised under control of the microprocessor 11. The vertical linear interpolator (VLI) 13 implements the calculation of interpolation based on the revised data in accordance with the following input/output relation. Subscript X of D is omitted. EQU Dy={(y.sub.M -y)D.sub.Y +yD.sub.Y+1 }/y.sub.M ( 1)
where y.sub.M is the number of scanning lines per vertical segment and it is supplied from the address signal generator 12 to the interpolator 13. In the above expression (1), variable Dy is the output of the interpolator 13, D.sub.Y and D.sub.Y+1 are data read out of the E.sup.2 PROM 10. The address signals X, Y and y are produced by the address signal generator 12 in the microprocessor 11. The microprocessor 11 stores the result Dy of the above expression (1) into the E.sup.2 PROM 14 by switching the input selection switches 7, 8 and 9 to the right position. The microprocessor 11 operates on these blocks through the control terminals, which are known in the art and are not shown in FIG. 2 for the purpose of simplicity.
Next, problems of the foregoing prior art will be described. A first drawback is the need of the expensive and capacious E.sup.2 PROM 14 for every format individually in constructing a multi-scan display unit, as mentioned previously. The reason for the provision of the memory for each format is a considerably long time expended for the calculation of the above expression (1). For example, when the microprocessor expends 1 ms for each calculation of the expression (1), the total time required for the calculation of one format is as follows. EQU 1 ms.times.16.times.1000.times.2 directions.times.3 colors.perspectiveto.96 sec
That is, it takes long time of about 96 sec.
The multi-scan display unit is required to display signals of different formats from various signal sources (computers) by switching from one picture to another momentarily (about 2 seconds or less), and therefore the 96-sec calculation time is unacceptable. To cope with this matter, the conventional display unit preparatively stores data of multiple formats in the E.sup.2 PROMs 14 and selects one memory momentarily. An alternative means is to replace the E.sup.2 PROMs with a single ROM. However, the required capacity for the single ROM is still too large as follows. EQU Required addresses=2.sup.7 (y).times.2.sup.7 (y.sub.M).times.2.sup.8 (D.sub.7).perspectiveto.4.times.10.sup.6
The address consists of 12 bits, and therefore a ROM with as large capacity as 48M bits is required.
A second drawback of the prior art is a clearly profiled unevenness of brightness emerging frequently in a reproduced picture on the display screen. FIG. 4 is a diagram analyzing the cause of uneven brightness encountered in the prior art. In the figure, shown by 23 is a graphical representation of Dy evaluated by the above expression (1), and its positive value signifies an ancillary deflection of a picture in the upward direction. Shown by 24 is a change in the density of scanning lines, i.e., a change in the brightness, caused by the ancillary deflection. FIG. 4 reveals that the brightness varies in steps each time the value of Y crosses a lattice point where it takes an integer (Y=1, 2, 3, . . . , n). The threshold of allowance of the step variation of brightness is about 3%. For example, in the case of 80 scanning lines per segment, with D.sub.1 and D.sub.3 being zero and D.sub.2 being 1.2 scanning line equivalently, the brightness increases by 1.5% in the segment between Y=1 and Y=2, and it decreases by 1.5% in the segment between Y=2 and Y=3, resulting in a step variation of 3% on the coordinate of Y=2. In other words, the brightness increases in the segment between Y=1 and Y=2 and the brightness decreases in the segment between Y=2 and Y=3, causing the emergence of uneven brightness in the area between Y=1 and Y=3. On this account, it is necessary to avoid a sharp step change in the brightness Ly in the example of FIG. 4.